ABOUT ME

Digital IC design engineer with {Loading Calculator} years of industry experience. The products include TDMA, LTE, NR modem, AI accelerator and high-speed IO(USB,HUB,DP). Skilled at low cost and low power IP design. Experienced in integration, front-end and middle-end design flow. Capable of building design verification environment in SystemVerilog & UVM.

EDUCATIONS

• Expertise field: memory integrated circuit designs
• Major in High-Speed Memory Sense Amplifier design
• Conducted Projects of SRAM, NV-TCAM, RRAM, NAND-Flash, 3D-TSV.

• Graduating in the honor of the top-rated prize
• Honorary membership of the phi tau phi scholastic honor society

EMPLOYMENT

SKILLS

• Programming language:
  Verilog-2005, SystemVerilog, Tcl, C/C++, Perl, Lua, Rust, Javascript, Typescript, SQL
• Tools:
  VCS, Xrun, Verdi, Simvision, DC, Genus, VC Formal, LEC, STA, SG-lint, SG-cdc, PTPX, Power-Artist
• Frameworks:
  UVM

PATENTS AND PUBLICATIONS

Published Papers:

• “A 256b-wordlength ReRAM-based TCAM with 1ns search-time and 14x improvement in wordlength-energyefficiency-density product using 2.5T1R cell ”IEEE International Solid-State Circuits Conference (ISSCC), Feb 2016.
• “Alow-powersubthreshold-to-superthresholdlevel-shifterforsub-0.5VembeddedresistiveRAM (ReRAM) macro in ultra low-voltage chips”IEEE Asia Pacific Conference on Circuit and Systems(APCCAS), Nov. 2014.

Patents:

• “Sense Amplifier”, United States Patent US 9378780 B1 Active Jun., 2015

SIDE PROJECTS

Register Abstration Layer Auto-Generator:

• Language: Javascript
• Description: User maintain an xlsx file and the tool will generate all needed files
• Input: Register information in xlsx format
• Output: Docx, html, json, rtl, header file, verification pattern
• Project Status: Released

Design Environment Generator:

• Language: Rust
• Description: Auto-generate ASIC design environment with executing command, tcls of tools, common ip and common verification blocks
• Support Tools: VCS, SpyGlass(lint, CDC), Design Compiler, Formality, Static-Analysis
• Project Status: Alpha Test

SystemVerilog Editor

• Language: Rust
• Description: A SystemVerilog text editor that supports syntax highlight, auto-correct, definition trace, declaration trace and auto complete
• Module Structure: A front-end text editor, a language server protocol and a back-end language server that includes tree-sitter and analyser
• Project Status: Developing