[SystemVerilog][Verification] Streaming Operators

The streaming operators "<<" and ">>" take an expression, structure, or array, and packs it into a stream of bits. ">>" streams data from left to right and "<<" streams data from right to left. Supports giving a slice size, which is used to break up the source before being streamed. Does not support assign the bit stream result directly to an unpacked array.

Source code:

---

initial begin
	int h;
	bit [7:0] b, g[4], j[4] = '{8'ha, 8'hb, 8'hc, 8'hd};
	bit [7:0] q, r, s, t;

	h = { >> {j}};                // 0a0b0c0d pack array into int
	h = { << {j}};                // b030d050 reverse bits
	h = { << byte {j}};           // 0d0c0b0a reverse bytes
	{>>{g}} = { << byte {j}};     // 0d, 0c, 0b, 0a unpack into array
	b = { << {8'b0011_0101}};     // 1010_1100 reverse bits
	b = { << 4 {8'b0011_0101}};   // 0101_0011 reverse nibble
	{ >> {q, r, s, t}} = j;       // Scatter j into bytes
	h = { >> {t, s, r, q}};       // Gather bytes into h
end

---

Converts between queues, but could also work with dynamic arrays.
Source code:

---

initial begin
	bit [15:0] wq[$] = {16'h1234, 16'h5678}; // wq[0] = 16'h1234
	bit [7:0]  bq[$];

	// Convert word array to byte
	bq = { >> {wq}}; // 12 34 56 78

	// Convert byte array to words
	bq = {8'h98, 8'h76, 8'h54, 8'h32};
	{ >> {wq}} = { >> {bq}}; // 9876 5432
end

---

Streaming operator to pack and unpack structures.
Source code:

---

initial begin
	typedef struct {
		int a;
		byte b;
		shortint c;
		int d;
	} my_struct_s;

	my_struct_s st = '{
		32'haaaa_aaaa,
		8'hbb,
		16'hcccc,
		32'hdddd_dddd
	};

	byte b[];

	// Covert from struct to byte array
	b = { >> {st} }; //{aa aa aa aa bb cc cc dd dd dd dd}

	// Convert from byte array to a struct
	b = '{8'h11, 8'h22, 8'h33, 8'h44, 8'h55 8'h66, 8'h77 8'h88, 8'h99, 8'haa, 8'hbb};
	st = { >> {b}}; // st = 11223344, 55, 6677, 8899aabb

end

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