Jui-Yu Hung
Mail: [email protected]
Digital IC design engineer with {Loading Calculator} years of industry experience. The products include TDMA, LTE, NR modem, AI accelerator, high-speed IO(USB,HUB,DP,PCIe) and HFT system. Skilled at low cost, low power and low latency design. Experienced in integration, front-end and middle-end design flow. Capable of building design verification environment in SystemVerilog & UVM.
National Tsing-Hua University
Taiwan
Master in EE
Jul. 2015
Bechelor in EE
Jun. 2013
VICI Holdings, Taiwan
HFT Digital Design Engineer
Dec.2024-NOW
Algoltek, Taiwan
ASIC Design Engineer
Apr.2022-Dec.2024
MemryX, Taiwan
ASIC Design Engineer
Sep.2020-Apr.2022
Mediatek, Taiwan
ASIC Design Engineer
Nov.2015-Sep.2020
Published Papers:
Patents:
Register Abstration Layer Auto-Generator:
Design Environment Generator:
SystemVerilog Editor